1. Field of the Invention
This invention relates to semiconductor memory devices, and more particularly to a system and method for testing semiconductor memory devices, prior to burn-in. Described herein are means for detecting device defects in the wafer sorting stage of production. Many such defects typically manifest themselves as hard failures in later production stages during operation at high temperatures, high voltages, or other types of stress testing. By screening these devices in early production, manufacturing costs are reduced and yields improved.
2. Description of the Related Art
The proliferation of computers and other microprocessor-based devices has contributed to an increasing demand for semiconductor memory. Microprocessors are present not only in computers, but in a diverse range of products including automobiles, cellular telephones and kitchen appliances. A conventional microprocessor executes a sequence of instructions and processes information. Frequently, both the instructions and the information reside in semiconductor memory. Therefore, an increased requirement for memory has accompanied the microprocessor boom. Furthermore, as microprocessors have become more sophisticated, greater capacity and speed are demanded from the associated memory.
There are various types of semiconductor memory, including Read Only Memory (ROM) and Random Access Memory (RAM). ROM is typically used where instructions or data must not be modified, while RAM is used to store instructions or data which must not only be read, but modified. ROM is a form of non-volatile storagexe2x80x94i.e., the information stored in ROM persists even after power is removed from the memory. On the other hand, RAM storage is generally volatile, and must remain powered-up in order to preserve its contents.
A conventional semiconductor memory device stores information digitally, in the form of bits (i.e., binary digits). The memory is typically organized as a matrix of memory cells, each of which is capable of storing one bit. The cells of the memory matrix are accessed by word lines and bit lines. Word lines are typically associated with the rows of the memory matrix, and bit lines with the columns. Raising a word line activates a given row; the bit lines are then used to read from or write to the corresponding cells in the currently active row. Memory cells are typically capable of assuming one of two voltage states (commonly described as xe2x80x9conxe2x80x9d or xe2x80x9coffxe2x80x9d). Information is stored in the memory by setting each cell in the appropriate logic state. For example, to store a bit having the value 1 in a particular cell, one would set the state of that cell to xe2x80x9conxe2x80x9d; similarly, a 0 would be stored by setting the cell to the off state. (Obviously, the association of on with 1 and off with 0 is arbitrary, and could be reversed.)
The two major types of semiconductor RAM, Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM), differ in the manner by which their cells represent the state of a bit. In an SRAM, each memory cell includes transistor-based circuitry that implements a bi-stable latch. A bi-stable latch relies on transistor gain and positive (i.e. reinforcing), feedback to guarantee that it can only assume one of two statesxe2x80x94on or off. The latch is stable in either state (hence, the term xe2x80x9cbi-stablexe2x80x9d). It can be induced to change from one state to the other only through the application of an external stimulus; left undisturbed, it will remain in its original state indefinitely. This is just the sort of operation required for a memory circuit, since once a bit value has been written to the memory cell, it will be retained until it is deliberately changed.
In contrast to the SRAM, the memory cells of a DRAM employ a capacitor to store the on/off voltage state representing the bit. A transistor-based buffer drives the capacitor. The buffer quickly charges or discharges the capacitor to change the state of the memory cell, and is then disconnected. Ideally, the capacitor then holds the charge placed on it by the buffer and retains the stored voltage level.
DRAMs have at least two drawbacks compared to SRAMs. The first of these is that leakage currents within the semiconductor memory are unavoidable, and act to limit the length of time the memory cell capacitors can hold their charge. Consequently, DRAMs typically require a periodic refresh cycle to restore sagging capacitor voltage levels. Otherwise, the capacitive memory cells would not maintain their contents. Secondly, changing the state of a DRAM memory cell requires charging or discharging the cell capacitor. The time required to do this depends on the amount of current the transistor-based buffer can source or sink, but generally cannot be done as quickly as a bi-stable latch can change state. Therefore, DRAMs are typically slower than SRAMs. DRAMs offset these disadvantages by offering higher memory cell densities, since the capacitive memory cells are intrinsically smaller than the transistor-based cells of an SRAM.
SRAMs are widely used in applications where speed is of primary importance, such as cache memory supporting the Central Processing Unit (CPU) in a personal computer. Like most semiconductor devices, SRAMs are fabricated en masse on semiconductor wafers, and subsequently sectioned and packaged. Early in the production process, a wafer sort test is performed. During this step, the individual SRAMs are electrically tested before sectioning the wafer. Any bad SRAMs that are identified at this stage will be discarded when the wafer is sectioned, thus avoiding the cost of packaging them.
Although the wafer sort succeeds in detecting hard failures, such as shorted address lines, there are more subtle defects that can go undetected until the SRAM is subjected to temperature cycling, operation at elevated voltages, or other types of stress testing. Among these is leakage between adjacent bit lines. Bit line-bit line leakage is often insufficient to cause the SRAM to fail preliminary functional testing during wafer sort, but tends to worsen with prolonged exposure to higher temperatures or higher voltages. Eventually, the magnitude of the leakage is great enough to cause the device to fail. Consequently, although bit line-bit line leakage is not presently detectable during wafer sort, it is thought to be a precursor to SRAM failures occurring during burn-in. Clearly, it would be desirable to have a method of detecting devices prone to this failure mode before going to the expense and trouble of packaging the SRAMs.
The problems outlined above may be addressed by a system and method disclosed herein for bit line-bit line defect detection in a semiconductor memory device. In the embodiments considered herein, the semiconductor memory device is a static random access memory (SRAM) device, but it is believed that the principles disclosed herein are applicable to other types of memory devices, as well. In fact, any memory device having adjacent bit lines may be suitable. As discussed herein, a semiconductor memory device is organized as an array of cells. The rows of the memory array may be accessed using word lines, and the columns (i.e., individual bits) may be accessed using complementary bit line pairs, each including lines BL and BLB. Thus, each combination of a word line and a bit line pair specifies an individual cell. SRAM memory cells may have complementary outputs (i.e., whenever one output is at logic level 1 the other is at logic level 0, and vice versa), each of which is coupled to one of the bit lines in the associated pair.
A system for testing a semiconductor memory device is disclosed herein, including first and second pairs of common lines, and first and second sets of bit lines. During leakage testing, the first common line may be connected to each of the first set of bit lines, and the other to each of the second set of bit lines. A voltage source applied between the common lines induces a current, the magnitude of which is related to the leakage resistance between adjacent bit lines. The bit lines are interleaved, such that each bit line from the first set is adjacent to a bit line from the second set. Moreover, each bit line from the first set is coupled to a first output of a respective memory cell, while each bit line from the second set is coupled to a second output of the memory cell. Furthermore, each of the first set of bit lines is connected to the first common line and each of the second set of bit lines is connected to the second common line, only when a test signal is active; at other times, first and second common lines are unconnected to the bit lines, and are instead connected to a fixed voltage by first and second shunt elements, respectively. Prior to performing a leakage measurement, all the cells within the semiconductor memory device are preset, such that the polarity of each of the first set of bit lines with respect to the adjacent bit line from the second set is the same as the polarity of the voltage source applied between the first and second common lines.
A method for testing a semiconductor memory device is also disclosed herein, including connecting first and second common lines to first and second sets of bit lines, respectively, and then measuring a resistance between the first and second common lines. In an embodiment of this method, the first and second sets of bit lines are interleaved, such that each bit line from the first set is adjacent to a bit line from the second set. Switches may be used to connect the bit lines from the first and second sets to first and second common lines, respectively, only when a test signal is active. In an embodiment, measuring constitutes applying. a voltage between the first and second common lines and measuring any resulting current. The voltage may be externally applied, or may originate from a voltage source within the memory device itself. In an embodiment of this method, first and second bit lines are coupled to complementary first and second outputs of a bi-stable latch within each memory cell, and the applied test voltage is approximately equal to the voltage across the latch. Prior to applying the test voltage, the memory cells are preset to the same logical value. In another embodiment, the first and second common lines are clamped to a fixed voltage, except during testing, by means of shunt devices within the memory device that are deactivated by the test signal.
A method for testing a semiconductor memory device is also disclosed, consisting of measuring the resistance between adjacent bit lines within the memory, prior to performing a stress test on the memory device. In an embodiment of this method, first and second sets of bit lines are coupled to first and second common lines, respectively, within the memory device, and then the resistance between the two common lines is measured.
A semiconductor memory device is also disclosed. In an embodiment, the semiconductor device contains an array of interleaved bit lines, with odd-numbered bit lines belonging to a first set and even-numbered bit lines belonging to a second set. A further feature of this embodiment is a complementary pair of common lines, such that the first common line is coupled to all the bit lines in the first set and the second common line is coupled to all the bit lines in the second set. Further, each bit line is coupled to a switch, which electrically connects the bit line to its respective common line only when a test signal is active. In one embodiment, the common lines are brought out to pads, allowing the application of an external voltage source to measure resistance between the common lines. Another embodiment of the semiconductor memory device disclosed herein is in the form of an integrated circuit.